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| 병행 o r r e 테스팅 | |||
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| A general hardware control that helps to detect data errors when data are read from memory or communicated from one computer to another (A 1-bit digit (either 0 or 1) is added to a data item to indicate whether the sum of that data item’s bit is odd or even. When the parity bit disagrees with the sum of the other bits, the computer reports an error. The probability of a parity check detecting an error is 50 percent) | |||
