Subject | English | Arabic |
comp., MS | advanced programmable interrupt controller | جهاز التحكم بالمقاطعة القابلة للبرمجة متقدم (A programmable interrupt controller (PIC) that provides multiprocessor interrupt management. An APIC incorporates both static and dynamic symmetric interrupt distribution across all processors. It usually has more available interrupt lines than a typical PIC) |
PSP | critical interrupt time | زمن القطع الحرج |
auto.ctrl. | interrupt capability | المقدرة على القطع |
auto.ctrl. | interrupt input unit | وحدة دخل إشارة القطع |
auto.ctrl. | interrupt reaction time | الزمن بين إشارتى القطع والقرار |
comp., MS | interrupt request | طلب إشارة المقاطعة (A signal sent by a device to get the attention of the processor when the device is ready to accept or send information) |
comp., MS | interrupt request line | خط طلب إشارة المقاطعة (A hardware line over which a peripheral device, bus controller, other processor, or the kernel signals a request for service to the microprocessor) |
comp., MS | interrupt service routine | روتين خدمة المقاطعة (A kernel-mode interrupt that is small, very fast pieces of assembly code that map physical interrupts onto logical interrupts. ISRs are used to provide hooks back to the kernel as well as device drivers) |
comp., MS | nonmaskable interrupt | إشارة مقاطعة ذات أولوية أعلى (A hardware interrupt that bypasses and takes priority over interrupt requests generated by software and by the keyboard and other such devices. A nonmaskable interrupt cannot be overruled (masked) by another service request and is issued to the microprocessor only in disastrous circumstances, such as severe memory errors or impending power failures) |
comp., MS | programmable interrupt controller | جهاز تحكم بالمقاطعة قابل للبرمجة (A device that functions as an overall manager in an interrupt driven system) |
comp., MS | system management interrupt | مقاطعة إدارة النظام (An interrupt generated by the host-controller-emulation hardware when a universal serial bus (USB) keyboard or mouse data is received and steered by the host controller hardware to a System Management Interrupt (SMI) or the standard host controller interrupt) |