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ещё совсем недавно большинство разработчиков рассматривали термин формальная верификация как синоним проверки на эквивалентность
stresses
progr.
in the not-so-distant past, the term formal verification was considered synonymous with equivalency checking for the majority of design engineers
(см.
'The Design Warrior's Guide to FPGAs' by Clive "Max" Maxfield
2004
)
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